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Bit
Name
Reset
Access
Description
Value
3
Mode
SET
Description
Set output on compare match
7:5
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
4
COIST
0
RW
Compare Output Initial State
This bit is only used in Output Compare and PWM mode. When this bit is set in compare mode,the output is set high when the counter
is disabled. When counting resumes, this value will represent the initial value for the output. If the bit is cleared, the output will be
cleared when the counter is disabled. In PWM mode, the output will always be low when disabled, regardless of this bit. However,
this bit will represent the initial value of the output, once it is enabled.
3
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
2
OUTINV
0
RW
Output Invert
Setting this bit inverts the output from the CC channel (Output compare,PWM).
1:0
MODE
0x0
RW
CC Channel Mode
These bits select the mode for Compare/Capture channel.
Value
0
1
2
3
Mode
OFF
INPUTCAPTURE
OUTPUTCOMPARE
PWM
Description
Compare/Capture channel turned off
Input capture
Output compare
Pulse-Width Modulation
19.5.13 TIMERn_CCx_CCV - CC Channel Value Register
Offset
0x034
Reset
Access
Name
Bit Position
Bit
Name
Reset
Access
Description
31:16
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
15:0
CCV
0x0000
RWH
CC Channel Value
In input capture mode, this field holds the first unread capture value. When reading this register in input capture mode, then contents
of the TIMERn_CCx_CCVB register will be written to TIMERn_CCx_CCV in the next cycle. In compare mode, this fields holds the
compare value.
2011-04-12 - d0001_Rev1.10
271
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